AMD Zen 6 Revealed: First Document Confirms Ground-Up Redesign on 2nm With Powerful New CPU Core

AMD Zen 6 Revealed: First Document Confirms Ground-Up Redesign on 2nm With Powerful New CPU Core

AMD has quietly published its first official document referencing the Zen 6 microarchitecture, and it reveals major architectural changes that go far beyond a simple generational upgrade. The document, titled “Performance Monitor Counters for AMD Family 1Ah Model 50h–57h Processors,” provides deep insight into upcoming Zen 6-based CPUs, including the data-center-focused EPYC “Venice” processors.

Unlike Zen 4 and Zen 5, Zen 6 is a clean-sheet design built on TSMC’s 2nm-class process. AMD confirms a wide, throughput-oriented architecture featuring a brand-new 8-wide dispatch engine paired with Simultaneous Multithreading (SMT). Two hardware threads dynamically share dispatch resources, prioritizing overall throughput rather than peak single-thread performance.

This approach may not always match the single-core strength of ultra-wide competitors, but it enables exceptionally high parallel performance. AMD even includes dedicated monitoring counters for dispatch slot usage, backend stalls, and SMT arbitration—clear signs the company is heavily investing in wide-issue efficiency.

Zen 6 also delivers a major leap in vector and floating-point performance. The architecture fully supports AVX-512 with FP64, FP32, FP16, and BF16 formats, along with FMA/MAC operations and mixed FP-INT workloads like VNNI, AES, and SHA. Sustained 512-bit execution throughput is high enough that AMD had to redesign performance counters to measure it accurately.

All signs point to Zen 6 being AMD’s first CPU architecture built primarily for data center workloads. While client implementations remain unknown, current evidence suggests Zen 6 CPUs will be exceptional number-crunching powerhouses.